Center for Digital and Analog Integrated Systems

Biblio

Found 156 results
Filters: Author is Sung-Mo Kang  [Clear All Filters]
2003
S. - M. Kang, “Elements of Low Power Design for Integrated Systems”, in IEEE International Symp. On Power Electronics and Design (ISPLED), 2003, pp. 205–210.
C. Kim, K.  W. Kim, and S. - M. Kang, “Energy Efficient Skewed Static Logic Design with Dual Vt”, IEEE Transactions on VLSI, vol. 11, pp. 64–70, 2003.
S. - M. Kang, G. Yang, and Z. Wang, “Gate-Leakage-Tolerant Circuits In Deep Sub-100nm CMOS Technologies”, in SPIE International Symposium on Microelectronics: Design, Technology, and Packaging, 2003, pp. 56–66.
K.  W. Kim, S.  O. Jung, T.  W. Kim, and S. - M. Kang, “Minimum Delay Optimization for Domino Logic Circuits - A Coupling-Aware Approach”, ACM Transactions on Design Automation of Electronic Systems, vol. 8, pp. 202–213, 2003.
S. Wu and S. - M. Kang, “Modeling and Time Domain Simulation of VCSEL using VHDL-AMS”, in IEEE Southwest Symposium on Mixed-Signal Design, 2003, pp. 170–174.
Y. S. Kim, S. H. Kim, K. - H. Baek, S. Kim, and S. - M. Kang, “Multiple Trigonometric Approximation of Sine-Amplitude for High Speed Direct Digital Frequency Synthesizers”, in International Symposium on VLSI, 2003, pp. 261–265.
G. Yang and S. - M. Kang, “A New Domino Failure Mechanism in Deep Sub-100nm Technologies and Its Solution”, in SPIE International Symposium on Microelectronics: Design, Technology, and Packaging, 2003, pp. 70–76.
K.  W. Kim, S.  O. Jung, U. Narayanan, C.  L. Liu, and S. - M. Kang, “Noise-Aware Interconnect Power Optimization in Domino Logic Synthesis”, IEEE Transactions on VLSI, vol. 11, pp. 79–89, 2003.
Q. Wang and S. - M. Kang, “An Optimal Design of Leak-Proof SRAM Cell Using MCDM Method”, in SPIE International Symposium on Microtechnologies for the New Millennium, 2003, pp. 478–484.
S. - O. Jung, K. Kim, and S. - M. Kang, “Timing Constraints for Domino Logic Gates with Timing-Dependent Keepers”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 96–104, 2003.
2002
E. Conforti, A.  C. Bordonalli, S.  H. Ho, and S. - M. Kang, “Carrier Reuse with Gain Compression and Feed-Forward Optical Amplifiers”, IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 77–81, 2002.
R.  K. Grube, Q. Wang, and S. - M. Kang, “Design Limitations in Deep Sub-0.1um CMOS SRAM Circuits for High-Performance On-Chip Cache Applications”, in IEEE Great Lakes Symposium on VLSI, 2002, pp. 94–97.
J. Chen, J. Zhou, C. Liu, and S. - M. Kang, “Development of a MEMs Vertical Planar Coil Inductor”, in Fifth International Conference on Modeling and Simulation of Microsystems, 2002, pp. 344–347.
K.  W. Kim, T.  W. Kim, C.  L. Liu, and S. - M. Kang, “Domino Logic Synthesis Based on Implication Graph”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 232–240, 2002.
S. - O. Jung, K. - W. Kim, and S. - M. Kang, “Dual Threshold Voltage Domino Logic Synthesis with Noise and Power Constraint”, in Design, Automation and Test in Europe (DATE), 2002, pp. 260–265.
S. - O. Jung and S. - M. Kang, “High Performance Dynamic Logic Incorporating Gate Voltage Controlled Keeper Structure for Wide Fan-In Gate”, IET Electronics Letters, vol. 38, pp. 852–853, 2002.
K.  W. Kim, T.  W. Kim, T.  T. Hwang, S. - M. Kang, and C.  L. Liu, “High-Speed CMOS Circuits with Parallel Dynamic Logic and Speed-Enhanced Skewed Static Logic”, IEEE Transactions on Circuits and Systems, vol. 49, pp. 434–439, 2002.
K.  W. Kim, T.  W. Kim, T.  T. Hwang, S. - M. Kang, and C.  L. Liu, “Logic Transformation for Low Power Synthesis”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 7, pp. 1–19, 2002.
G. Yang, S. - O. Jung, S. H. Kim, and S. - M. Kang, “A Low-Power 2.1 GHz 32-bit Carry Lookahead Adder Using Dual Path All-N-Logic”, in IEEE International Midwest Symposium on Circuits and Systems, 2002, pp. 298–301.
C. Kim, I. Hwang, and S. - M. Kang, “Low-Power Small-Area ±7.28ps Jitter 1GHz DLL-Based Clock Generator”, in IEEE International Solid-State Circuits Conference, 2002, pp. 142-143.
C. Kim, I. Hwang, and S. - M. Kang, “Low-Power Small-Area ±7.28ps Jitter 1GHz DLL-Based Clock Generator”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1414–1420, 2002.
S. - O. Jung, K. - W. Kim, and S. - M. Kang, “Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages”, in ACM/IEEE Design Automation Conference, 2002, pp. 467–472.
C. Kim and S. - M. Kang, “A low-swing clock double-edge triggered flip-flop”, IEEE Journal of Solid-State Circuits, vol. 37, pp. 648–652, 2002.
K.  H. Baek, M. - J. Choe, and S. - M. Kang, “A Low-Voltage High-Speed BICMOS Current Switch With Enhanced-Spectral Performance”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2002, pp. 53–56.
S.  O. Jung, K.  W. Kim, and S. - M. Kang, “Noise Constrained Power Optimization for Dual Vt Domino Logic”, IEEE Transactions on VLSI, vol. 10, pp. 532–541, 2002.

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