Center for Digital and Analog Integrated Systems

Biblio

Found 156 results
Filters: Author is Sung-Mo Kang  [Clear All Filters]
2002
I. Hwang and S. - M. Kang, “A Self-Regulating VCO with Supply Sensitivity 0.15%-delay/1%-supply”, in IEEE International Solid-State Circuits Conference, 2002, pp. 140-141.
S. - O. Jung and S. - M. Kang, “Skew-Tolerant High Performance Domino Logic”, in International Symposium on VLSI, 2002, pp. 41–46.
J. Lee, K. - W. Kim, and S. - M. Kang, “VeriCDF: A New Verification Methodology for Charged Device Failures”, in ACM/IEEE Design Automation Conference, 2002, pp. 874–879.
2001
S.  M. Yoo, S.  O. Jung, and S. - M. Kang, “2-Level LFSR scheme with Asynchronous Test Pattern Transfer for Low Cost and High Efficiency Built-In-Self-Test”, in ACM 11th Great Lakes Symposium on VLSI, 2001.
S. - M. Kang and S. - M. Yoo, “Circuit Solutions for Overcoming Ultra-deep Submicron CMOS Leakage Currents, Noises and Power Consumption”, in International Technical Conference on Circuits, Systems, Computers and Communications(ITC-CSCC), 2001, pp. 1–4.
K. - W. Kim, S. - O. Jung, P. Saxena, C. L. Liu, and S. - M. Kang, “Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique”, in IEEE Design Automation Conference(DAC), 2001, pp. 732–737.
K.  W. Kim, S.  O. Jung, T.  W. Kim, and S. - M. Kang, “Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits”, Electronics Letters, vol. 37, pp. 813–814, 2001.
K.  W. Kim, S.  O. Jung, and S. - M. Kang, “Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 371–374.
K. Kim and S. - M. Kang, “Crosstalk Noise Minimization in Domino Logic Design”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, pp. 1091–1100, 2001.
J. Lee, Y. Huh, P. Bendix, and S. - M. Kang, “Design-for-ESD-Reliability in High-Frequency I/O Interfaces in Deep-Submicron CMOS Technology”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 746–749.
I. - C. Hwang and S. - M. Kang, “Differential Pass-Transistor Clocked Flip-flop”, Electronics Letters, vol. 37, pp. 732–734, 2001.
J. Chen and S. - M. Kang, “Dynamic Macromodeling of MEMS Mirror Devices”, in IEEE International Electron Device Meeting(IEDM), 2001, pp. 41.5.1–41.5.4.
Q. Li and S. - M. Kang, “Efficient Algorithms for Polygon to Trapezoid-to-Simple Polygon Recomposition for Resistance Extraction”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 495–498.
C. Kim, K.  W. Kim, and S. - M. Kang, “Energy Efficient Skewed Static Logic Design with Dual Vt”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 882–885.
Q. Li, Y.  J. Huh, J.  W. Chen, P. Bendix, and S. - M. Kang, “ESD Design Rule Checker”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 499–502.
Q. Li, Y.  J. Huh, J.  W. Chen, P. Bendix, and S. - M. Kang, “Full Chip ESD Design Rule Checking”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 503–506.
S.  M. Yoo, S.  O. Jung, and S. - M. Kang, “Low Cost and High Efficinet BIST Scheme with 2-Level LFSR and APTP”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 1–4.
K. - H. Baek, M. - J. Choe, C. Souza, and S. - M. Kang, “A Low Glitch SiGe BiCMOS Current Switch for High Performance D/A Converters”, in 44th Midwest Symposium on Circuits and Systems, 2001, pp. 606–609.
C. Kim and S. - M. Kang, “A Low-Power Reduced Swing Single Clock Flip-Flop”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 806–809.
C. Kim and S. - M. Kang, “A Low-Swing Clock Double-Edge Triggered Flip-Flop”, in IEEE International Symposium on VLSI, 2001, pp. 183–186.
J. Chen and S. - M. Kang, “Model-Order Reduction of Nonlinear MEMS Devices Through Arclength-Based Karhunen-Loeve Decomposition”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 457–460.
I.  C. Goknar, H. Kutuk, and S. - M. Kang, “MOMCO: Method of Moment Components for Passive Model Order Reduction of RLCG Interconnects”, IEEE Transactions on Circuits and Systems, vol. 48, pp. 459–474, 2001.
S.  M. Yoo, C.  W. Kim, S.  O. Jung, K.  H. Baek, and S. - M. Kang, “New Current-mode Sense Amplifier for High Density DRAM and PIM Architectures”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 938–941.
S.  O. Jung, K.  W. Kim, and S. - M. Kang, “Noise Constrained Power Optimization for Dual Vt Domino Logic”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 158–161.
J. Lee, Y. Huh, P. Bendix, and S. - M. Kang, “Noise-Aware Design for ESD Reliability in Mixed-Signal Integrated Circuits”, in 14th IEEE International ASIC/SOC Conference, 2001, pp. 437–441.

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