Center for Digital and Analog Integrated Systems

Biblio

Found 19 results
Filters: Author is K. W. Kim  [Clear All Filters]
2003
K.  W. Kim, S.  O. Jung, P. Saxena, C.  L. Liu, and S. - M. Kang, “Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique”, IEEE Transactions on VLSI, vol. 11, pp. 879–887, 2003.
C. Kim, K.  W. Kim, and S. - M. Kang, “Energy Efficient Skewed Static Logic Design with Dual Vt”, IEEE Transactions on VLSI, vol. 11, pp. 64–70, 2003.
K.  W. Kim, S.  O. Jung, T.  W. Kim, and S. - M. Kang, “Minimum Delay Optimization for Domino Logic Circuits - A Coupling-Aware Approach”, ACM Transactions on Design Automation of Electronic Systems, vol. 8, pp. 202–213, 2003.
K.  W. Kim, S.  O. Jung, U. Narayanan, C.  L. Liu, and S. - M. Kang, “Noise-Aware Interconnect Power Optimization in Domino Logic Synthesis”, IEEE Transactions on VLSI, vol. 11, pp. 79–89, 2003.
2002
K.  W. Kim, T.  W. Kim, C.  L. Liu, and S. - M. Kang, “Domino Logic Synthesis Based on Implication Graph”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 232–240, 2002.
K.  W. Kim, T.  W. Kim, T.  T. Hwang, S. - M. Kang, and C.  L. Liu, “High-Speed CMOS Circuits with Parallel Dynamic Logic and Speed-Enhanced Skewed Static Logic”, IEEE Transactions on Circuits and Systems, vol. 49, pp. 434–439, 2002.
K.  W. Kim, T.  W. Kim, T.  T. Hwang, S. - M. Kang, and C.  L. Liu, “Logic Transformation for Low Power Synthesis”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 7, pp. 1–19, 2002.
S.  O. Jung, K.  W. Kim, and S. - M. Kang, “Noise Constrained Power Optimization for Dual Vt Domino Logic”, IEEE Transactions on VLSI, vol. 10, pp. 532–541, 2002.
2001
K.  W. Kim, S.  O. Jung, T.  W. Kim, and S. - M. Kang, “Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits”, Electronics Letters, vol. 37, pp. 813–814, 2001.
K.  W. Kim, S.  O. Jung, and S. - M. Kang, “Coupling-Aware Minimum Delay Optimization for Domino Logic Circuits”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 371–374.
C. Kim, K.  W. Kim, and S. - M. Kang, “Energy Efficient Skewed Static Logic Design with Dual Vt”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 882–885.
S.  O. Jung, K.  W. Kim, and S. - M. Kang, “Noise Constrained Power Optimization for Dual Vt Domino Logic”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 158–161.
S.  O. Jung, S.  M. Yoo, K.  W. Kim, and S. - M. Kang, “Skew-Tolerant High-Speed (STHS) Domino Logic”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2001, pp. 154–157.
S.  O. Jung, K.  W. Kim, and S. - M. Kang, “Transistor Sizing for Reliable Domino Logic Design in Dual Threshold Voltage Technologies”, in ACM 11th Great Lakes Symposium on VLSI, 2001.
2000
K.  W. Kim, K.  H. Baek, N. Shanbhag, C.  L. Liu, and S. - M. Kang, “Coupling-Driven Signal Encoding Schemes for Low-Power Interface Design”, in IEEE International Conference on Computer-Aided Design (ICCAD), 2000, pp. 318–321.
K.  W. Kim, U. Narayanan, and S. - M. Kang, “Domino Logic Synthesis Minimizing Crosstalk”, in IEEE Design Automation Conference(DAC), 2000, pp. 280–285.
K.  H. Baek, K.  W. Kim, and S. - M. Kang, “EXODUS: An Inter-Module Bus-Encoding Scheme for System-On-A-Chip”, Electronics Letters, vol. 36, pp. 615–617, 2000.
K.  H. Baek, K.  W. Kim, and S. - M. Kang, “A Low Energy Encoding Technique for Reduction of Coupling Effects in SoC Interconnects”, in IEEE 43rd Midwest Symposium on Circuits and Systems (MWSCAS), 2000, pp. 80–83.
K.  W. Kim, S.  O. Jung, U. Narayana, C.  L. Liu, and S. - M. Kang, “Noise-Aware Power Optimization for On-Chip Interconnect”, in International Symposium on Low Power Electronic and Design, 2000, pp. 108–113.