Center for Digital and Analog Integrated Systems

Biblio

Found 2 results
Filters: Author is N. Venkateswaran  [Clear All Filters]
2005
M.  R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov, “Gate Sizing Using Incremental Parameterized Statistical Timing Analysis”, in International Workshop on Logic Synthesis (IWLS), 2005.
M. Guthaus, N. Venkateswaran, and V. Zolotov, “Optimization objectives and models of variation for statistical gate sizing”, in Great Lakes Symposium on VLSI (GLSVLSI), 2005.