Center for Digital and Analog Integrated Systems

Biblio

Found 211 results
2011
W. Condley, A. W. Hill, and M. R. Guthaus, “Advanced Logic Design through Hands-On Digital Music Synthesis”, in International Conference on Microelectronics Education (MSE), 2011, pp. 17–20.
X. Hu and M.  R. Guthaus, “Clock Tree Optimization for Electromagnetic Compatibility (EMC)”, in Asia and South Pacific Design Automation Conference (ASPDAC), 2011, pp. 184–189.
C. - M. Jung, E. - S. Lee, K. - S. Min, and S. - M. Kang, “Compact Verilog-A model of phase-change RAM transient behaviors for multi-level applications”, Semiconductor Science and Technology, vol. 26, p. 105018, 2011.
S. Shin, K. Kim, and S. - M. Kang, “Complementary Structure of Memristive Devices Based Passive Memory Arrays”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 321–324.
M.  R. Guthaus, “Distributed LC Resonant Clock Tree Synthesis”, in International Symposium on Circuits and Systems (ISCAS), 2011, pp. 1215–1218.
X. Hu and M.  R. Guthaus, “Distributed Resonant Clock Grid Synthesis (ROCKS)”, in Design Automation Conference (DAC), 2011, pp. 516–521.
K. Kim, S. Shin, and S. - M. Kang, “Field Programmable Stateful Logic Array”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 1800-1813, 2011.
S. Kim and M. R. Guthaus, “Leakage-Aware Redundancy for Reliable Sub-threshold Memories”, in Design Automation Conference (DAC), 2011, pp. 435–440.
S. Kim and M. R. Guthaus, “Low-Power Multiple-Bit Upset Tolerant Memory Optimization”, in International Conference on Computer-Aided Design (ICCAD), 2011.
S. Shin, K. Kim, and S. - M. Kang, “Memristor Applications For Programmable Analog ICs”, IEEE Transactions on Nanotechnology, vol. 10, pp. 266–274, 2011.
K. Eshraghian, K. - R. Cho, O. Kavehei, S. - K. Kang, D. Abbott, and S. - M. Kang, “Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines”, IEEE Transactions on Very Large Scale Integration Systems, vol. 19, pp. 1407–1417, 2011.
W. Condley, X. Hu, and M. R. Guthaus, “A Methodology for Local Resonant Clock Synthesis using LC-Assisted Local Clock Buffers”, in International Conference on Computer-Aided Design (ICCAD), 2011.
J. - H. Bong, K. - H. Jo, K. - S. Min, and S. - M. Kang, “Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits”, Journal of Low Power Electronics, vol. 7, pp. 87–95, 2011.
S. Logan and M.  R. Guthaus, “Package-Chip Co-Design to Increase Flip-Chip C4 Reliability”, in International Symposium on Quality Electronic Design (ISQED), 2011, pp. 553–558.
S. Shin, K. Kim, and S. - M. Kang, “Reconfigurable Stateful NOR Gate for Large-Scale Logic Array Integrations”, IEEE Transactions on Circuits and Systems II, vol. 58, pp. 442–446, 2011.
R. Chipana, L. F. Kastensmidt, J. Tonfat, R. Reis, and M. Guthaus, “SET Susceptibility Analysis in Buffered Tree Clock Distribution Networks”, in Conference on Radiation Effects on Components and Systems (RADECS), 2011, pp. 256-261.
S. Kim and M. R. Guthaus, “SNM-Aware Power Reduction and Reliability Improvement in 45nm SRAMs”, in International Conference on Very Large Scale Integration of System-on-Chip (VLSISOC), 2011.
K. Kim, S. Shin, and S. - M. Kang, “Stateful Logic Pipeline Architecture”, in IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 2497–2500.
M.  R. Guthaus, “What is resonant clocking?”, ACM SIGDA E-Newsletter, ACM SIGDA, 2011.
2010
W. Condley, X. Hu, and M.  R. Guthaus, “Analysis of High-Performance Clock Networks with RLC and Transmission Line Effects”, in System Level Interconnect Prediction Workshop (SLIP), 2010, pp. 51–58.
D. Chan and M.  R. Guthaus, “Analysis of Power Supply Induced Jitter in Actively De-skewed Multi-Core Systems”, in International Symposium on Quality Electronic Design (ISQED), 2010, pp. 785–790.
S. Shin, K. Kim, and S. - M. Kang, “Compact Models for Memristors”, in 2nd Memristor and Memristive Systems Symposium, 2010.
S. Shin, K. Kim, and S. - M. Kang, “Compact Models for Memristors Based on Charge-Flux Constitutive Relationships”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, pp. 590–598, 2010.
S. Shin, K. Kim, and S. - M. Kang, “Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices”, IEEE Transactions on Circuits and Systems II, vol. 57, pp. 986–990, 2010.
J. - H. Park, S. Shin, J. Christofferson, A. Shakouri, and S. - M. Kang, “Experimental Validation of the Power Blurring Method”, in Semiconductor Thermal Measurement, Modeling, and Management Symposium (Semi-Therm 26), 2010, pp. 240–244.

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